By Michael Keating
Reuse method handbook for System-on-a-Chip Designs, 3rd version outlines a suite of top practices for growing reusable designs to be used in an SoC layout method. those practices are in keeping with the authors' event in constructing reusable designs, in addition to the adventure of layout groups in lots of businesses all over the world. Silicon and power applied sciences movement so quick that a few of the information of design-for-reuse will absolutely proceed to adapt over the years. however the basic facets of the technique defined during this booklet became extensively followed and tend to shape the root of chip layout for a while to come.
Development technique unavoidably differs among method designers and processor designers, in addition to among DSP builders and chipset builders. despite the fact that, there's a universal set of difficulties dealing with every body who's designing advanced chips. according to those difficulties, layout groups have followed a block-based layout method that emphasizes layout reuse. Reusing macros (sometimes known as "cores") that experience already been designed and validated is helping to handle all the difficulties above. in spite of the fact that, in adopting reuse-based layout, layout groups have run right into a major challenge. Reusing blocks that experience no longer been explicitly designed for reuse has frequently supplied very little profit to the crew. the hassle to combine a pre-existing block into new designs can turn into prohibitively excessive, if the block doesn't give you the correct perspectives, the perfect documentation, and the best functionality.
From this adventure, layout groups have learned that reuse-based layout calls for an particular method for constructing reusable macros which are effortless to combine into SoC designs. This handbook specializes in describing those recommendations. good points of the 3rd variation:
- Up up to now;
- State of the artwork;
- Reuse as an answer for circuit designers;
- A chronicle of "best practices";
- All chapters up-to-date and revised;
- Generic directions - non device particular;
- Emphasis on difficult IP and actual design.