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By Philipp Klaus Krause (auth.), Ranjit Jhala, Koen De Bosschere (eds.)

ISBN-10: 3642370500

ISBN-13: 9783642370502

ISBN-10: 3642370519

ISBN-13: 9783642370519

This publication constitutes the lawsuits of the twenty second foreign convention on Compiler development, CC 2013, held as a part of the eu Joint meetings on idea and perform of software program, ETAPS 2013, which happened in Rome, Italy, in March 2013. The thirteen papers provided during this ebook have been rigorously reviewed and chosen from fifty three submissions. they've been equipped into 5 topical sections on sign in allocation, pointer research, facts and data circulate, laptop studying, and refactoring.

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Extra resources for Compiler Construction: 22nd International Conference, CC 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013. Proceedings

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Our algorithm is based on Click’s aggressive Global Code Motion (GCM) algorithm [Cli95]. We use an example to illustrate the differences between GCM and GCMS. Figure 1(a) shows a small program in SSA form adapted from the original paper on GCM. It is easy to see that the computation of variable b is loop-invariant and can be hoisted out of the loop; further, the computation for d is not needed until after the loop. Since the value of its operand i2 is available at the end of the loop, we can sink this multiplication to the end Optimal and Heuristic Global Code Motion for Minimal Spilling 23 block.

In: ICS 1988: Proceedings of the 2nd International Conference on Supercomputing, pp. 442–452. : Minimum register instruction sequencing to reduce register spills in out-of-order issue superscalar architectures. : Nearly Optimal Register Allocation with PBQP. -M. ) JMLC 2006. LNCS, vol. 4228, pp. 346–361. : Combined Code Motion and Register Allocation Using the Value State Dependence Graph. In: Hedin, G. ) CC 2003. LNCS, vol. 2622, pp. 1–16. : Software pipelining: an effective scheduling technique for VLIW machines.

This allows us to apply our optimization to Fortran programs from the SPEC CPU 2000 benchmark suite as well. Unfortunately, our version of Dragonegg miscompiles six of the SPEC benchmarks, but this still leaves us with 20 benchmarks to evaluate. We generate code for the ARM Cortex-A9 architecture with VFP3 hardware floating 34 G. Barany and A. Krall point support and use the -O3 optimization flag to apply aggressive optimizations both at the intermediate code level and in the backend. The overlap analysis was implemented using SWI-Prolog, and we use CPLEX as our ILP solver.

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Compiler Construction: 22nd International Conference, CC 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013. Proceedings by Philipp Klaus Krause (auth.), Ranjit Jhala, Koen De Bosschere (eds.)


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